The disclosed invention relates to digital computers, and more particularly to the architecture thereof. Many types of digital computers exist in the prior art. Basically however, the architecture for these computers can be classified into two categories. One category includes those computers which are totally hardwired and have no control store memory, while the other category includes those computers which are microprogrammed and have a control store memory.
Computers which do not have a control store memory have an architecture which is highly irregular. This is because these computers consist solely of a plurality of logic gates and flip-flops which are interconnected in multiple complex combinations. The multiple combinations are necessary if the computer is to execute an entire instruction set. A problem with these computers is that as the instructions set grows in size, so does the complexity of the interconnection between the gates and flip-flops which comprise the machine. This makes them difficult to design and difficult to maintain.
In comparison, processors which have a control store are relatively regular in structure. Basically, the control store provides a means for storing therein thousands of relatively simple microcommands. The hardwired logic gates and flip-flops in these computers execute these relatively simple commands. Since the commands are relatively simple, so is the logic required to implement them. Conversely, the microcommands are arranged in complex programs in the control store, and the programs execute higher level language instructions for the computer user. That is, each command of the high level language is implemented by a program of multiple microinstructions within the control store of the computer.
One problem however, with some computers having a control store is that their operation is undesirably slow. To overcome this problem, some prior art computers having a control store implement their microinstructions in a hardwired pipeline. Basically, this pipeline consists of several hardwired stages; and each stage performs a portion of the microcommand. This architecture decreases the execution time of the microcommands, since it provides a means for executing the microcommands in an overlapped fashion. For example, in a two stage pipeline, one stage of the pipeline will be executing one microcommand while the other stage of the pipeline will be fetching the next microcommand to be executed. A problem with these computers however, is that each of the stages are comprised of hardwired special purpose logic which increases the complexity and irregularity of the machine.
A technique for increasing the speed of operation even further in a computer having a hardwired pipeline is to increase the complexity of the microcommands themselves. That is, as each microcommand is made to do more things, a smaller number of them are required to be combined to form the programs which execute the instructions of the higher level language. Accordingly, the high level language instructions execute faster. A problem with this approach however, is that as the microinstructions become more complex, so does the hardware which is required to implement them. As a result, a computer having both a hardwired pipeline and a complex microinstruction set no longer resembles a regular structure. Instead it is often more complex than a completely hardwired computer.
It is therefore one object of the invention to provide an improved architecture for a digital computer.
Another object of the invention is to provide a pipelined computer having stages which consist of the same identical hardware.
Another object of the invention is to provide a pipelined computer having stages which are separate microprogrammed computers.
Another object of the invention is to provide a pipelined computer having stages which individually are pipelined computers.
Still another object of the invention is to provide a pipelined computer having stages which individually are comprised of microprogrammed computers with writable control stores.